Prior to SystemVerilog, users were forced to use a hardware description language (HDL – usually either Verilog or VHDL) to describe their design, a separate hardware verification language (HVL) to describe the testbench, and a separate proprietary assertion language. This three-pronged approach has led to isolated environments, requiring design and verification engineers to become specialists in a particular aspect of the methodology and its accompanying language, at the expense of efficiency and communication between teams.
This tutorial will cover all aspects of SystemVerilog and show how unifying testbench, design and assertions allows:
• Enhanced modeling constructs for more concise design descriptions at multiple levels of abstraction
• Object-oriented and constrained-random data generation capabilities for advanced testbenches
• Integrated assertions for specifying temporal properties to bring formal verification and simulation together.
Although all of these capabilities are available today with separate languages, this tutorial will stress the advantages of integration.
After discussing the fundamentals of the language, the tutorial will focus on developing a methodology for verification that exploits the interoperability of the features built into SystemVerilog. Methodology components to be covered include:
• Creating a layered testbench environment for constrained-random stimulus generation, self-checking transactors, and test automation at multiple levels of abstraction
o Use of object-oriented coding techniques to modify and extend test scenarios without having to rewrite known-good code.
o The use of interface encapsulation to isolate components from changes in abstraction level of other components in the system.
• Coverage definition, recording and analysis, including functional and code coverage metrics, that can be reported and correlated across multiple tools.
• Design for Verification – Designers participating more fully in verification
o Integrating assertions into the design and verification flow, allowing designers to capture intent to provide additional power for verification.
Including a library of pre-verified assertion checker components
The use of SystemVerilog assertions with VHDL
o Sharing of verification concepts (ie. waiting for event sequences to complete) to allow designers to write better block-level tests.
• Coverage driven test generation - Automation and orchestration to increase the functional coverage automatically, using formal and hybrid technologies.